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FMS7951
Zero Delay Clock Multiplier
Features
* * * * * * * * * Low Voltage CMOS or PECL reference input Up to 175 MHz of output frequency Nine configurable outputs Output enable pin 250 pS of output to output skew 300 pS of Cycle to Cycle Jitter VDD Range of 3.3V 0.2V Commercial temperature range Available in 32 pin TQFP
It has four banks of configurable outputs. By externally connecting one of the outputs to FBIN, the internal PLL will lock in both phase and frequency to the incoming clock. Any changes to the input clock will be tracked by the outputs. Depending on the selected output for feedback connection, the output frequencies will be as 1X, 2X or 4X of the input. REF_SEL allows selection between PECL input or TCLK a CMOS clock driven input. Connecting PLL_EN LOW and REF_SEL HIGH will by pass the Phase locked loop. In this mode, FMS7951 will be in clock buffer mode where any clock applied to TCLK will be divided down to the four output banks. This is ideal for system diagnostic test. When PLL_EN is HIGH, the PLL is enabled, and any clock applied to TCLK will be locked in both phase and frequency to FBIN. PECL_CLK is activated when REF_SEL is high. FMS7951 operates at 3.3 Volts and is available in 32 pin LQFP.
Description
FMS7951 is a high speed, zero delay, low skew clock driver. It uses phase locked loop technology to generate frequencies up to 175 MHz.
Block Diagram
REF_SEL PLL_EN OE
TCLK QA MUX MUX PECL_CLK PECL_CLK FBIN QC1 QD0 QD1 DIV_SEL A QD2 DIV_SEL B DIV_SEL C DIV_SEL D QD4 Control Logic PLL QC0 QB
QD3
REV. 1.0.0 1/9/01
PRODUCT SPECIFICATION
FMS7951
Pin Assignments
REF_SEL GNDOUT QA VDDOUT GNDOUT PLL_EN TCLK
VDDCOR FBIN DIV_SEL A DIV_SEL B DIV_SEL C DIV_SEL D GNDCOR PECL_CLK
1 2 3 4 5 6 7 8
32 31 30 29 28 27 26 25 24 23 22 32-PIN LQFP 21 20 19 18 17 9 10 11 12 13 14 15 16 GNDOUT PECL_CLK OE VDDOUT QD3 VDDOUT QD4 QD2
QB
QC0 VDDOUT QC1 GNDOUT QD0 VDDOUT QD1 GNDOUT
Pin Description
Pin Name VDDCOR FBIN DIV_SEL(A:D) GNDCOR PECL_CLK/ PECL_CLK OE VDDOUT Pin # 1 2 3, 4, 5, 6 7 8, 9 10 11, 15, 19, 23, 27 Pin Type PWR IN IN PWR IN IN PWR OUT PWR IN IN IN Description Power Connection. Power supply for core logic and PLL circuitry. Connect to 3.3 Volts nominal. Feedback In. PLL feedback input. The user connects it to one of the outputs. Divider Select: It divides the clock to a desirable value. See table 2. No internal pull up or pull down. Ground Connection. Ground for core logic and PLL circuitry. Connect to the common system ground plane. PECL Clock Input: These are differential PECL inputs when REF_SEL is Low, they are activated. Output Enable. When high, all outputs are in high impedance. Normal operation when asserted low. Power Connection. Power supply for all the output buffers. Connect to 3.3 Volts nominal. Clock Outputs. These outputs are multiple of the input. Ground Connection. Ground for all the outputs. Connect to common system ground plane. Test Clock. When PLL-EN is low, all outputs are buffer copy of TCLK. PLL Enable. When low, PLL is by passed. Reference Select. When low, PECL_CLK/PECL_CLK is used for input. When high, TCLK is used for input.
QA; QB; QC(0:1); 12, 14, 16, 18, 20, 22, 24, 26, 28 QD(0:4) GNDOUT TCLK PLL_EN REF_SEL 13, 17, 21, 25, 29 30 31 32
2
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FMS7951
PRODUCT SPECIFICATION
Table 1. Functionality
REF_SEL 0 0 0 1 1 1 PLL_EN 0 0 1 0 0 1 OE 1 0 0 1 0 0 PLL By Pass By Pass Enabled By Pass By Pass Enabled All Outputs Hi-Z Running Running Hi-Z Running Running Input PECL_CLK PECL_CLK PECL_CLK TCLK TCLK TCLK
Table 2. Input Versus Output Frequency
DIV_SELA 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 DIV_SELB 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 DIV_SELC 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DIV_SELD 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 QA 2XREF 4XREF 2XREF 4XREF 2XREF 4XREF 2XREF 4XREF REF 2XREF REF 2XREF REF 2XREF REF 2XREF QB REF 2XREF REF 2XREF 1/2REF REF 1/2REF REF REF 2XREF REF 2XREF 1/2REF REF 1/2REF REF QC REF 2XREF 1/2REF REF REF 2XREF 1/2REF REF REF 2XREF 1/2REF REF REF 2XREF 1/2REF REF QD REF REF REF REF REF REF REF REF REF REF REF REF REF REF REF REF
Note: 1. Reference input could be either PECL_CLK or TCLK input. 2. FBIN is tied to QD output for table
Table 3. Divide Select Functionality
DIV_SEL A 0 1 DIV_SEL B 0 1 DIV_SEL D 0 1 DIV_SEL D 0 1 QA /2 /4 QB /4 /8 QC /4 /8 QD /4 /8
REV. 1.0.0 1/9/01
3
PRODUCT SPECIFICATION
FMS7951
Absolute Maximum Ratings
Symbol VDD, VIN TSTG TB TA Parameter Voltage on any pin with respect to ground Storage Temperature Ambient Temperature Operating Temperature Ratings -0.5 to 7.0 -65 to 150 -55 to 125 0 to 70 Units V C C C
Stresses greater than those listed in the table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may effect reliability.
DC Electrical Characteristics
TA = 0 to 70C; Supply Voltage 3.3 V 0.2V (unless otherwise stated) Parameter Input Low Voltage Input High Voltage Input Low Current Input High Current Peak to Peak Input Voltage Common Mode Range Output Low Voltage Output High Voltage Input Capacitance(1) Supply Current Clock Stabilization(1) Symbol VIL VIH IIL IIH VPP VCMR VOL VOH CIN IDD TSTAB Outputs loaded From VDD = 3.3V to 1% Target TBD IOL= 40 mA IOH= -40mA 2.2 7.0 150 10 Conditions TCLK; control pins TCLK; control pins VIN= 0 VIN= VDD PECL_CLK/PCL_CLK 2.0 -10 -30 0.3 VDD-2.0 Min. Typ. Max. 0.8 3.6 10 30 1.0 VDD-0.6 0.5 Units V V A A V mV V V pF mA mS
Note: 1. Guaranteed by design, not subject to 100% production testing.
AC Electrical Characteristics
TA = 0 to 70C; Supply Voltage VDD = 3.3V 0.2V, CL = 10 pF (unless otherwise stated) Parameter Input Frequency Symbol FIN Conditions Feedback Divide = 2 Feedback Divide = 4 Feedback Divide = 8 TCLK Input Rise/Fall Time TCLK Input Duty Cycle
(1) (1)
Min. 10 10 10 - 25
Typ.
Max. 175 85 42 3.0 75 175 88 750
Units MHz
TR_IN/TF_IN DT_IN FOUT QA; DIV_SEL A = 0V QB, QC & QD; DIV_SEL B, C, D = 0V
ns % MHz MHz pS
Output Frequency Range
Output to Output Skew Input to FBIN Delay
TSK1 TSK2
VTH = VDD/2; DIV_SEL A = 0 VTH = VDD/2; DIV_SEL A = 1 TCLK PECL_CLK -300 50 -950
300 400 -600 pS
4
REV. 1.0.0 1/9/01
FMS7951
PRODUCT SPECIFICATION
AC Electrical Characteristics (Cont.) TA = 0 to 70C; Supply Voltage VDD = 3.3V 0.2V, CL = 10 pF (unless otherwise stated)
Parameter Rise Time(1) Fall Time(1) Cycle(1) Duty Symbol TR TF DT TJIT Conditions 0.8 to 2.0V 2.0 to 0.8V VTH = VDD/2 QA: DIV_SEL A = 0 QA: DIV_SEL A = 1 QB Output QC(0:1) Outputs QD(0:4) Outputs
Note: 1. Guaranteed by design, not subject to 100% production testing.
Min. 0.10 0.10 45
Typ.
Max. 1.0 1.0 55 450 200 200 300 375
Units nS nS % pS
Jitter (Cycle-Cycle)
REV. 1.0.0 1/9/01
5
PRODUCT SPECIFICATION
FMS7951
Parameter Measurement Information
Duty Cycle (DT)
T1 T2 DT = 1.5V 1.5V 1.5V T2 x 100 T1
Rise/Fall Time (TR/TF)
2.0V Output 0.8V 2.0V 0.8V 0V 3.3V
TR
TF
Output to Output Skew (TSK1)
1.5V Q0 1.5V Any Output TSK1
Input to Output Delay (TSK2)
1.5V TCLK
1.5V FBIN TSK2
PECL_CLK PECL_CLK
6
REV. 1.0.0 1/9/01
FMS7951
PRODUCT SPECIFICATION
Mechanical Dimensions
32-Pin LQFP
Inches Min. A A1 A2 B C D/E D1/E1 e L N ND ccc - Max. 0.063 0.006 0.057 Millimeters Min. - Max. 1.60 0.15 Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982. 2. Dimensions "D1" and "E1" do not include mold protrusion. 3. Pin 1 identifier is optional. 4. Dimension N: number of terminals. 7 5. Dimension ND: Number of terminals per package edge. 6. "L" is the length of terminal for soldering to a substrate. 7. "B" includes lead finish thickness. 2 6 4 5
Symbol
0.002 0.053 0.012 0.018 - 0.004 0.354 BSC 0.276 BSC 0.032 BSC 0.018 0.030 32 8 0 7 - 0.004
0.05 1.35 1.45 0.30 0.45 - 0.10 9.00 BSC 7.00 BSC 0.800 BSC 0.45 0.75 32 8 0 7 - 0.10
D D1
e
E E1
PIN 1 IDENTIFIER C
L .039" Ref (1.00mm)
See Lead Detail A A2 B A1 Seating Plane Base Plane -CLEAD COPLANARITY ccc C
REV. 1.0.0 1/9/01
7
PRODUCT SPECIFICATION
FMS7951
Ordering Information
Product Number FMS7951KWC FMS7951KWCX Package Description LQFP-32 LQFP-32 w/T+R Package Marking 7951KWC 7951KWC
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com 1/9/01 0.0m 003 Stock#DS3007951 2000 Fairchild Semiconductor Corporation

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